Serial Peripheral Interface – SPI protocol

Serial Peripheral Interface – SPI is a serial, master-slave protocol. SPI is a single master protocol wherein the other slave cannot become master during any stage of communication. SPI uses 4 wires for the communication between the master and the slave. Clock(CLK), MOSI(Master Out Slave In), MISO(Master In Slave Out) and SS(Slave Select) are the four lines used for communication. SPI baud rate is configurable. The max baud rate can be configured up to the peripheral bus frequency divided by 2 in case of Cortex (example: In case of ARM Cortex 4 series of micro-controllers, if the SPI is connected on the APB1 bus and the APB bus can is running at 42 MHz then SPI can run at 21 MHz).

Communication between the master and the slave can start only after the master has activated the slave it want to communicate with. MOSI lines is used by the master for data transmission to the slave and MISO for receiving data from the slave. Data transmission or reception on the MOSI or the MISO line is done in sync with either the rising or the falling edge of the clock. Clock can only be initiated by the master and has to be kept active for the complete duration of the communication.

SPI is a full-duplex protocol but can be configured as per the requirement. As per the requirement, SPI can be configured only for TX, only for RX or as bi-directional wherein the same line can be used as MOSI and MISO. The possible available configurations have to be checked in the controller manual. If bi-directional configuration is used, there are two phases called the MOSI phase and the MISO phase.

The communication between the master and the slave begins with the master pulling the SS line low and starting the CLK. After starting the CLK the master can send the data on the MOSI line. As SPI is a full duplex protocol, with every transmission of data byte the master also receives a byte of data on the MISO line. If no data is available on the MISO line, the master will read all ‘0’s. When the master has to receive data from the slave, the master has to keep the clock active till the number of bytes required are received by the master.

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